1. Field of the Invention
The present invention relates to a multiprocessor system having a memory commonly used by the processors. More particularly, the processors are operated under a time division control mode.
2. Description of the Related Art
A multiprocessor system is comprised of a plurality of processors, for example, microprocessors. The processors are usually used for performing so-called load distribution. Therefore, the related multiprocessor system can carry a heavy load, i.e., many peripheral terminal equipment.
In general, the multiprocessor system contains, other than the processors, memories, data buses, and so on. From an economic viewpoint, it is preferable not to mount individual memories for each processor, but to mount a single memory for common use by these processors. This is also true of the data buses, i.e., a single time division data bus is preferably employed and distributed between the common memory and the processors.
Common usage of the memory is preferable from an economic viewpoint but suffers from the problem of write operations to the memory being often commanded from the processors simultaneously. Two or more simultaneously read operations to the memory are possible, but two or more simultaneous write operations cause the serious trouble of erasure of significant data stored therein. That is, when one of the processors writes data in the memory, the remaining processors must be inhibited from their respective write operations and must wait until they are allowed to use the memory.
In the prior art, the inhibition from the write operation is established with the use of both a halt signal line and a start signal line. When one of the processors, i.e., a master processor, is going to write data to the memory, the memory first applies a halt signal to the remaining processors, i.e., slave processors, in a case where, for example, an initial program loading (IPL) is to be executed. Therefore, during the execution of the IPL by the master processor, the slave processors cannot be operated due to the halt signal transferred, via the halt signal line, from the main processor. When the execution of the IPL is completed, the main processor applies the start signal to allow the slave processors to start operating. The slave processors then watch a flag concerned to determine whether or not the flag indicates that the slave processors are now operable. The flag is written in the memory by the master processor. If the flag indicates the slave processors can operate, then these slave processors can start executing individual jobs.
However, there is a problem in the prior art multiprocessor system, that is, the slave processors can no longer operate once the halt signal is issued from the master processor. That is, the slave processors are left in an idle state during the provision of the halt signal. Such an idle state clearly causes a loss in throughput of the overall multiprocessor system.